1. Technical Field of the Invention
The technology described herein relates generally to high-capacity communication networks. More specifically, the technology relates to optical networks.
2. Description of Related Art
Increasing network traffic in communication backbone networks has recently resulted in the need to upgrade the current infrastructure. Tremendous growth in network traffic requirements has increased the need for a high-capacity network backbone between service providers and subscribers. One solution to the increased traffic requirements is provided by Passive Optical Networks (PONs). PONs support an inexpensive, simple, scalable system that leverages the existing, low-cost Ethernet technology with optic network architecture.
A PON is a single, shared optical fiber that uses optical splitters to divide the single fiber into separate fibers feeding individual subscribers. Each subscriber has a dedicated fiber that converges together with other subscriber fibers at a common site where they share an Optical Distribution Network (ODN) trunk fiber back to a central location. By incorporating optical splitters, the need for electrical equipment is eliminated. Additionally, the amount of fiber required for PON configurations is less than that of traditional point-to-point topological networks.
Standard PON configurations involve a passive connection between an optical line terminal (OLT) coupled to a network and a plurality of optical network units (ONU). Data is transferred from the OLT to ONU through a single, shared fiber. Passive optical splitters (POS) located downstream of the OLT feed the data to a plurality of ONUs that are coupled to individual subscribers.
A PON apparatus typically consists of an upstream network media access control (MAC) port at the OLT adapted to transmit/receive data to/from the upstream network. The upstream MAC port provides MAC and physical coding sublayer (PCS) functions. Compatibility of the transmitted frames between the OLT and the ONU is achieved through a Logical Link Identification (LLID). The LLID identifies a flow to an ONU using an 8 byte preamble of the Ethernet frame that is attached during transmission of the data from the OLT. A second MAC port is provided at the ONU connected to the physical interface and configured to process frames transmitted from the OLT.
Media Access Control elements are required at both ends of the network. A PON MAC provides data processing capabilities, management features and quality of service (QOS) functions. They are typically instantiated on a per port basis such that an octal port device has 8 instances of the MAC. FIG. 1 illustrates an example of an Ethernet PON (EPON) OLT 100 featuring a quad 10 Gbps/1 Gbps port having switch 101 in connection with lanes 102-1-102-N. Each lane consists of at least a 1 Gbps MAC 103, a 10 Gbps MAC 104 and scheduler (SCH) 105 connected to dynamic bandwidth allocator (DBA) 106. Each lane also contains the necessary PCS components 107 (e.g., line interface modules, advance encryption standard chip(s) (e.g., China Telecom Triple Churning Encryption), forward error correction (FEC) such as 1G, 10G and physical coding sublayer (XPCS) for encoding and processing individual data streams. Inputs/Outputs (I/O) from the EPON lanes are transferred using, for example, using serializer/deserializer (SERDES) 108.
A serializer/deserializer (SERDES) converts data between serial data and parallel interfaces in each direction. The term “SERDES” generically refers to interfaces used in various technologies and applications. The basic SERDES function is made up of two functional blocks: a Parallel In, Serial Out (PISO) block (aka Parallel-to-Serial converter) and a Serial In, Parallel Out (SIPO) block (aka Serial-to-Parallel converter).
The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external Phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also have a double-buffered register.
The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. The receive clock may have been recovered from the data by the serial clock recovery technique. However, SERDES which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side. Such serializer encoder and deserializer decoder blocks are generally defined in the Gigabit Ethernet specification.
Although effective, the EPON OLT described above occupies a large physical space and consumes a relatively large amount of power. The technology described herein provides for a channelized MAC that can support 4 ports while substantially reducing the area of the EPON MAC.
The following IEEE standards/draft standards, as well as any additional standards described herein, are hereby incorporated herein by reference in their entirety and are made part of the present U.S. Utility patent application for all purposes:                1. IEEE Stds 802.3##™ (generically), “IEEE Standard for Information technology—IEEE 802.3 is a working group and a collection of IEEE standards produced by the working group defining the physical layer and data link layer's media access control (MAC) of wired Ethernet. This is generally a local area network technology with some wide area network applications. Physical connections are made between nodes and/or infrastructure devices (hubs, switches, routers) by various types of copper or fiber cable. 802.3 is a technology that supports the IEEE 802.1 network architecture. 802.3 also defines LAN access method using CSMA/CD.        2. IEEE Std 802.3ah™, “IEEE Standard for Information Technology—IEEE 802.3ah defines Multi-Point Control Protocol (MPCP), Point-to-Point Emulation (P2PE), and two 1490/1310 nm PMDs for 10 and 20 km, required to build an EPON system.        3. IEEE Std 802.3av™, “IEEE Standard for Information Technology—IEEE 802.3av defines 10 Gbit/s Ethernet Passive Optical Network. The standard supports two configurations: symmetric, operating at 10 Gbit/s data rate in both directions, and asymmetric, operating at 10 Gbit/s in the downstream direction and 1 Gbit/s in the upstream direction.        
Disadvantages of conventional approaches will be evident to one skilled in the art when presented in the disclosure that follows.